1. Field of the Invention
The present invention relates to a clock adjust circuit, a shift detection circuit, an imaging device and a clock adjustment method capable of detecting and adjusting a shift in a duty ratio of a clock signal.
2. Description of the Related Art
Clock signals are heretofore used for controlling operations in various electronic apparatuses. For example, clock signals are supplied also to circuits such as a counter and a DAC (Digital to Analog Converter) in solid-state imaging devices such as a CIS (Contact Image Sensor) (for example, refer to JP-A-2005-323331 (Patent Document 1)).
Here, FIG. 15 shows a circuit block configuration on the periphery of the counter used in the related-art solid-state imaging device, for example, proposed in Patent Document 1. In the related-art solid-state imaging device, a clock signal (internal clock) having a given duty ratio generated by a clock generation unit 201 is supplied to a DAC 203 and a counter 204 through a buffer 202. In such solid-state imaging device, the counter 204 is driven by a DDR (Double Data Rate) system to generate a high-definition as well as high-frame rate video signal.
The operation outline performed when the counter 204 is driven by the DDR system will be explained reference to FIG. 16. FIG. 16 is a schematic block configuration diagram of the DDR-driven counter 204. The DDR-driven counter 204 includes a first latch 205 and a second latch 206. The clock signal (CLK in FIG. 16) is inputted to one input terminal of the first latch 205 and a data signal (Data in FIG. 16) is inputted to the other input terminal. Additionally, the clock signal is inputted to one input terminal of the second latch 206 through a NOT element 207 (inverter) and the data signal is inputted to the other input terminal.
When the counter 204 is DDR-driven, counting processing is performed at both timings of rising and falling of the clock signal to be inputted. Specifically, the first latch 205 latches data when triggered by rising of the clock signal, and the second latch 206 latches data when triggered by falling of the clock signal. Then, the data latched by the second latch 206 is used as the least significant bit of the counter 204.
In the counter 204 having the above configuration, a trigger cycle in which data is latched by the first latch 205 and the second latch 206 is desired to be half of the cycle of the clock signal. That is, the duty ratio of the clock signal at the time of driving the counter 204 in the DDR system is ideally desired to be 50%.
In the present specification, “duty ratio” of the clock signal means the ratio of a high-level period occupied in one cycle of the clock signal, which can be calculated by [H-width/clock signal cycle]×100%. Hereinafter, the high-level period and a low-level period of the clock signal are referred to as an H-period and an L-period and values of the time width of the H-period and the L-period are referred to as an H-width and an L-width.